Clock signal generator for an integrated circuit

ABSTRACT

A clock signal generator which is particularly useful for a double data rate SDRAM (DDR-SDRAM) includes two or more clock signal input buffers and an enable signal input buffer. The clock signal generator generates internal clock signals that fluctuate at substantially different timings, yet the relationship between the internal clock signals with respect to validation and invalidation timing is constant. A latch circuit latches an enable signal from the enable signal buffer in accordance with a first internal clock signal from a first one of the clock signal buffers. A first enable signal connected to the latch circuit holds the latched enable signal in accordance with the first internal clock signal. A second enable circuit receives the first enable signal and the first internal clock signal and generates a second enable signal used to activate the clock signal buffers. A logic gate receives the first enable signal and the first internal clock signal and controls the output of the first internal clock signal.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to semiconductor integratedcircuits, and more particularly, to a clock signal generator for asemiconductor integrated circuit that generates clock signals having aplurality of differing phases.

[0002] A conventional synchronous dynamic random access memory (SDRAM)generates an internal clock signal using external clock signals sentfrom an SDRAM controller and provides the internal clock signal tointernal circuits. The SDRAM validates and invalidates the internalclock signal in accordance with an external power-down signal (clockenable signal) sent from the SDRAM controller. More specifically, thegeneration of the internal clock signal is stopped if the externalpower-down signal is low regardless of whether the external clock signalis provided. The internal clock signal is generated from the externalclock signal when the external power-down signal is high.

[0003]FIG. 1 is a schematic block diagram illustrating an internal clocksignal generating circuit 100. The generating circuit 100 receives anexternal clock signal CLK and an external power-down signal (clockenable signal) CKE and uses these signals to generate an internal clocksignal CLKMZ. Furthermore, the generating circuit 100 includes a clocksignal input buffer 91, a power-down signal input buffer 92, a clocksignal monitor input buffer 93, a latch circuit 94, and an enable signalgenerating circuit 95.

[0004] The clock signal input buffer 91, which is preferably a currentmirror type input buffer, receives the external clock signal CLK from anSDRAM controller and provides each internal circuit (not shown) with theclock signal CLKMZ, which phase is substantially the same as theexternal clock signal CLK. The buffer 91 is activated by a high enablesignal ENZ and deactivated by a low enable signal ENZ. Thus, the buffer91 outputs the internal clock signal CLKMZ if the enable signal ENZ ishigh and inhibits the output of the internal clock signal CLKMZ when theenable signal ENZ is low regardless of whether the external clock signalCLK is provided, as shown in FIG. 2. The enable signal ENZ is generatedby the power-down signal input buffer 92, the clock signal monitor inputbuffer 93, the latch circuit 94, and the enable signal generatingcircuit 95.

[0005] The power-down signal input buffer 92, which is preferably acurrent mirror type input buffer, receives the external power-downsignal CKE from the SDRAM controller and generates a main power-downsignal CKEMZ, which phase is substantially the same as the externalpower-down signal CKE. That is, the buffer 92 outputs a high mainpower-down signal CKEMZ if the external power-down signal CKE is high(non-power-down state) and outputs a low main power-down signal CKEMZ ifthe external power-down signal CKE is low (power-down state).

[0006] The clock signal monitor input buffer 93, which is preferably acurrent mirror type input buffer, receives the external clock signal CLKfrom the SDRAM controller and generates a monitor internal clock signalCLKSZ, which phase is substantially the same as the external clocksignal CLK. The buffer 93 is activated when either the main power-downsignal CKEMZ or the enable signal ENZ is high and deactivated when boththe main power-down signal CKEMZ and the enable signal ENZ are low.Thus, the buffer 93 outputs the monitor internal clock signal CLKSZ whenactivated and inhibits the output of the monitor internal clock signalCLKSZ when deactivated regardless of whether the external clock signalCLK is provided, as shown in FIG. 2.

[0007] The latch circuit 94 latches the main power-down signal CKEMZwhen the monitor internal clock signal CLKSZ goes high and outputs thelatched main power-down signal CKEMZ as the internal power-down signalCKECZ. Thus, the latch circuit 94 outputs a high or low internalpower-down signal CKECZ when the monitor internal clock signal CLKSZgoes high.

[0008] The enable signal generating circuit 95 latches the internalpower-down signal CKECZ when the monitor internal clock signal CLKSZgoes low and outputs the latched internal power-down signal CKECZ as theenable signal ENZ. Furthermore, the generating circuit 95 outputs thepreviously latched internal power-down signal CKECZ as the enable signalENZ when the monitor internal clock signal CLKSZ goes high. In otherwords, the generating circuit 95 outputs a delayed low enable signal ENZwhen the internal power-down signal CKECZ goes low and outputs a delayedhigh enable signal ENZ when the internal power-down signal CKECZ goeshigh. Therefore, the clock signal input buffer 91 outputs the internalclock signal CLKMZ when the enable signal ENZ, or the internalpower-down signal CKECZ, is high. On the other hand, the buffer 91 doesnot output the internal clock signal CLKMZ when the internal power-downsignal CKECZ is low.

[0009] A double-data-rate (DDR)-SDRAM has been proposed to satisfy therecent demand for increasing the speed of a data bus and an SDRAM. TheDDR-SDRAM includes a clock signal generating circuit for receiving twoexternal clock signals, each having a phase which differs by 180° fromthe other, and generating two internal clock signals, each having aphase which differs by 180° from the other, using the two external clocksignals. The DDR-SDRAM further includes a first internal circuit sectionoperated in accordance with a first internal clock signal and a secondinternal circuit section operated in accordance with a second internalclock signal. Data processing is divided between the first and secondinternal circuit sections to increase the operating speed of theDDR-SDRAM.

[0010] In the DDR-SDRAM, it is preferred that the two internal clocksignals fluctuate at substantially different timings and that therelationship of the two internal clock signals with respect to thevalidation and invalidation timing is always constant. In other words,if the relationship between the first and second internal clock signalsis always constant, for example, if the first internal clock signal isalways validated or invalidated before the second internal clock signal,the number of processes executed by the first internal circuit sectionis the same as that executed by the second internal circuit section.Accordingly, the first and second internal circuit sections alwaysexecute processes under the same conditions.

[0011] If the validation and invalidation timings of the first andsecond internal clock signals change intermittently, the number ofprocesses executed by the first internal circuit section is differentfrom that executed by the second internal circuit section. This resultsin the processing conditions of the first internal circuit sectiondiffering from those of the second internal circuit section and hinderssatisfactory processing.

[0012] The two internal clock signals are generated by two externalclock signal input buffers. The external clock signal input buffers areactivated by a high power-down signal and deactivated by a lowpower-down signal. Thus, the validation or invalidation timing of eachinternal clock signal is determined by the power-down signal.

[0013] However, the shifting of the power-down signal between a highlevel and a low level is carried out without regard to the externalclock signal. Thus, when the power-down signal is shifted, the firstinternal clock signal may be validated or invalidated before or afterthe second internal clock signal. That is, the validation andinvalidation timings of the first and second internal clock signalschanges in accordance with the power-down signal. Therefore, therelationship between the first and second internal clock signals withrespect to the validation and invalidation timing is not alwaysconstant.

[0014] Accordingly, it is an objective of the present invention toprovide a semiconductor integrated circuit that always validates andinvalidates two internal clock signals with a constant relationship.

SUMMARY OF THE INVENTION

[0015] To achieve the above objective, the present invention provides asemiconductor integrated circuit. The integrated circuit includes aplurality of clock signal input circuits. Each clock signal inputcircuit receives a respective one of plurality of external clock signalsand generates a respective one of plurality of internal clock signals.An external control signal input circuit receives an external controlsignal and generates an internal control signal. An output controlcircuit receives the internal control signal from the external controlsignal input circuit and controls the output of the internal clocksignals in accordance with changes in the internal control signal.

[0016] In a further aspect of the present invention, a semiconductorintegrated circuit includes a first-clock signal input buffer and asecond clock signal input buffer for receiving first and second externalclock signals, each having a different phase, and generating first andsecond internal clock signals, each having a different phase,respectively. A power-down signal input buffer receives an externalpower-down signal and generates an internal power-down signal. An outputcontrol circuit receives the internal power-down signal from thepower-down signal input buffer and controls the output of the first andsecond internal clock signals in accordance with changes in the internalpower-down signal.

[0017] In another aspect of the present invention, A semiconductorintegrated circuit includes a plurality of clock signal input circuits,including at least a first clock signal input circuit and a second clocksignal input circuit, for receiving a respective plurality of externalclock signals, and generating a respective plurality of internal clocksignals therefrom. An external control signal input circuit receives anexternal control signal and generates an internal control signal used toactivate the plurality of clock signal input circuits. A latch circuitconnected to the external control signal input circuit and the firstclock signal input circuit latches the internal control signal inresponse to a first internal clock signal generated by the first clocksignal input circuit. A first enable signal generating circuit,connected to the latch circuit and the first clock signal input circuit,holds the latched internal control signal in response to the firstinternal clock signal and generates a first enable signal. A gatecircuit, connected to the first enable signal generating circuit and thefirst clock signal input circuit, receives the first enable signal andthe first clock signal and controls the output of the first clock signalin accordance with the first enable signal. A second enable signalgenerating circuit, connected to the first enable signal generatingcircuit and the first clock signal input circuit, receives the firstenable signal and the first internal clock signal and generates a secondenable signal. The second enable signal is provided to the first andsecond clock signal input circuits to control the output of the firstand second internal clock signals.

[0018] Other aspects and advantages of the present invention will becomeapparent from the following description, taken in conjunction with theaccompanying drawings, illustrating by way of example the principles ofthe invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The invention, together with objects and advantages thereof, maybest be understood by reference to the following description of thepresently preferred embodiments together with the accompanying drawingsin which:

[0020]FIG. 1 is a schematic block diagram showing a conventionalinternal clock signal generating circuit;

[0021]FIG. 2 is a timing chart showing the operation of the internalclock signal generating circuit of FIG. 1;

[0022]FIG. 3 is a schematic block diagram showing a DDR-SDRAM accordingto a first embodiment of the present invention;

[0023]FIG. 4 is a schematic block diagram showing an internal clocksignal generating circuit of the DDR-SDRAM of FIG. 3;

[0024]FIG. 5 is a circuit diagram showing a first clock signal inputbuffer of the internal clock signal generating circuit of FIG. 4;

[0025]FIG. 6 is a circuit diagram showing a second clock signal inputbuffer of the internal clock signal generating circuit of FIG. 4;

[0026]FIG. 7 is a circuit diagram showing a latch circuit of theinternal clock signal generating circuit of FIG. 4;

[0027]FIG. 8 is a circuit diagram showing a first enable signalgenerating circuit of the internal clock signal generating circuit ofFIG. 4;

[0028]FIG. 9 is a circuit diagram showing a second enable signalgenerating circuit of the internal clock signal generating circuit ofFIG. 4;

[0029]FIG. 10 is a timing chart showing the operation of the internalclock signal generating circuit of FIG. 4;

[0030]FIG. 11 is a circuit diagram showing a further example of thesecond enable signal generating circuit of FIG. 9;

[0031]FIG. 12 is a schematic block diagram showing an internal clocksignal generating circuit according to a second embodiment of thepresent invention;

[0032]FIG. 13 is a schematic block diagram showing an internal clocksignal generating circuit employed in a third embodiment according tothe present invention;

[0033]FIG. 14 is a timing chart showing the operation of the internalclock signal generating circuit of FIG. 13;

[0034]FIG. 15 is a schematic block diagram showing an internal clocksignal generating circuit according to a fourth embodiment of thepresent invention; and

[0035]FIG. 16 is a timing chart showing the operation of the internalclock signal generating circuit of FIG. 15.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] In the drawings, like numerals are used for like elementsthroughout.

[0037] [First Embodiment]

[0038]FIG. 3 is a schematic block showing a DDR-SDRAM 200 employed in afirst embodiment according to the present invention. The DDR-SDRAM 200includes a clock buffer circuit 1, a command decoder circuit 2, anaddress buffer circuit 3, an input-output data circuit 4, a controlsignal latch circuit 5, a mode resistor circuit 6, a column addresscounter circuit 7, a delay locked loop (DLL) circuit 8, and a DRAM corecircuit 9.

[0039] The clock buffer circuit 1 receives an external power-down signalCKE and first and second external clock signals CLK1, CLK2, which phasesdiffer from each other by 180°, from an external device (not shown).When the external power-down signal CKE is high (non-power-down state),the clock buffer circuit 1 outputs first and second internal clocksignals CLKM1, CLKM2, the phases of which are substantially the same asthe first and second external clock signals CLK1, CLK2, respectively.When the external power-down signal CKE is low (power-down state), theclock buffer circuit 1 inhibits the output of the first and secondinternal clock signals CLKM1, CLKM2. The external power-down signal CKEand the first and second internal clock signals CLKM1, CLKM2 are sent tothe command decoder circuit 2 and the DLL circuit 8.

[0040] The command decoder circuit 2 receives an external command COM,which includes a column address strobe signal CAS, a write enable signalWE, a chip select signal CS, a row address strobe signal RAS, and anauto precharge enable signal AP from the external device in accordancewith the first and second internal clock signals CLKM1, CLKM2. Thecommand decoder circuit 2 decodes the external command COM based on thestatus (high or low) of each of the signals CAS, WE, CS, RAS, AP and inaccordance with the external power-down signal CKE and the first andsecond clock signals CLKM1, CLKM2 to generate commands, such as a writecommand, a read command, and a refresh command. The command decodercircuit 2 sends the decoded commands, as an internal command and anenable signal, to the address buffer circuit 3, the input-output datacircuit 4, the control signal latch circuit 5, and the mode resistorcircuit 6.

[0041] The address buffer circuit 3 receives address signals A₀-A₁₁ andbank addresses BA₀-BA₁ from the external device in accordance with theinternal command, which is sent from the command decoder circuit 2.Further, the address buffer circuit 3 sends address data derived fromthe address signals A₀-A₁₁ and the bank addresses BA₀-BA₁ to the controlsignal latch circuit 5, the mode resistor circuit 6, and the columnaddress counter circuit 7. The address buffer circuit 3 also sends rowaddress data derived from the address signals A₀-A₁₁ to the DRAM corecircuit 9.

[0042] The input-output data circuit 4 is activated by the enable signalfrom the command decoder circuit 2 and receives a data strobe signalDQS, write data DQ₀-DQ₇, and a data mask signal DM from the externaldevice. The input-output data circuit 4 latches the write data DQ₀-DQ₇in response to the rising and falling of the data strobe signal DQS andsends the latched write data DQ₀-DQ₇ to the DRAM core circuit 9.Furthermore, the input-output data circuit 4 sends the read data DQ₀-DQ₇from the DRAM core circuit 9 to the external device in accordance withthe internal command from the command decoder circuit 2.

[0043] The control signal latch circuit 5 receives the internal commandfrom the command decoder circuit 2 and the address data from the addressbuffer circuit 3, writes the write data of the DRAM core circuit 9 inaccordance with the internal command and the address data, reads theread data, and provides control signals for performing operations, suchas refreshing and self-refreshing.

[0044] The mode resistor circuit 6 receives the internal command fromthe command decoder circuit 2 and the address data from the addressbuffer circuit 3 and maintains the processing mode of the DRAM corecircuit 9 in accordance with the internal command and the address data.

[0045] The column address counter circuit 7 receives the column addressdata, which is derived from the address signals A₀-A₁₁ from the addressbuffer circuit 3 and sends the column address data to the DRAM corecircuit 9 in accordance with the mode maintained by the mode resistorcircuit 6.

[0046] The DLL circuit 8 receives the first and second internal clocksignals CLKM1, CLKM2 from the clock buffer circuit 1 and generates clocksignals having different frequencies. The clock signals are sent to theinput-output data circuit 4.

[0047] The DRAM core circuit 9 receives the row address data from theaddress buffer circuit 3, control signals from the control signal latchcircuit 5, and the column address data from the column address countercircuit 7. The DRAM core circuit 9 writes the write data on a memorycell array in accordance with the control signals and the address data,reads the read data, and performs processes such as refreshing andself-refreshing. That is, the DRAM core circuit 9 writes the write dataDQ₀-DQ₇ on a memory cell at predetermined addresses in accordance withthe control signals and the address data.

[0048]FIG. 4 is a schematic block diagram showing an internal clocksignal generating circuit 10 a, which is incorporated in the clockbuffer circuit 1. The generating circuit 10 a generates the first andsecond internal clock signals CLKM1, CLKM2 from the first and secondexternal clock signals CLK1, CLK2, respectively. The internal clocksignal generating circuit 10 a includes a first clock signal inputbuffer 11, a second clock signal input buffer 12, a power-down signalinput buffer 13, a latch circuit 14, a first enable signal generatingcircuit 15, a second enable signal generating circuit 16, and a firstgate circuit 17. The first and second clock signal input buffers 11, 12function as clock signal input circuits. The power-down signal inputbuffer 13 functions as an external control signal input circuit.Furthermore, the latch circuit 14, the first enable signal generatingcircuit 15, the second enable signal generating circuit 16, and thefirst gate circuit 17 function as output control circuits of the firstand second internal clock signals.

[0049] The first clock signal input buffer 11 receives the firstexternal clock signal CLK1 from the external device and outputs a firstclock signal CLKSZ, which phase is substantially the same as the firstexternal clock signal CLK1. Furthermore, the first clock signal inputbuffer 11 is activated when either a main-power down signal CKEMZ, whichis sent from the power-down signal input buffer 13, or a second enablesignal ENZ2, which is sent from the second enable signal generatingcircuit 16, is high. The first clock signal input buffer 11 isdeactivated when the main power-down signal CKEMZ and the second enablesignal ENZ2 are both low.

[0050]FIG. 5 is a circuit diagram showing the first clock signal inputbuffer 11, which includes a differential amplifying circuit 11 a and acontrol circuit 11 b. The differential amplifying circuit 11 a is acurrent mirror type circuit and is provided with a differentialamplifying portion having n-channel MOS (NMOS) transistors Q1, Q2, aconstant current portion having an NMOS transistor Q3, and a currentmirror portion having p-channel MOS (PMOS) transistors Q4, Q5.

[0051] The sources of the NMOS transistors Q1, Q2 are grounded by way ofthe NMOS transistor Q3. The drain of the NMOS transistor Q1 is connectedto a high potential power supply by way of the PMOS transistor Q4. Thedrain of the NMOS transistor Q2 is connected to a high potential powersupply by way of the PMOS transistor Q5. The gates of the transistorsQ4, Q5 are connected together and to the drain of the NMOS transistorQ2. The drain of the NMOS transistor Q1 is connected to an invertercircuit 21. The gate of the NMOS transistor Q1 is provided with thefirst external clock signal CLK1. The gate of the NMOS transistor Q2 isprovided with a reference voltage Vref. The gate of the NMOS transistorQ3 is provided with a control signal CON, which is generated by thecontrol circuit 11 b.

[0052] The control circuit 11 b includes a transfer gate 22 having aPMOS transistor and an NMOS transistor, a PMOS transistor Q6, and aninverter circuit 23. The PMOS transistor gate of the transfer gate 22 isprovided with the main power-down signal CKEMZ, while the NMOStransistor gate of the transfer gate 22 is provided with the mainpower-down signal CKEMZ by way of the inverter circuit 23. If the mainpower-down signal CKEMZ is low, the transfer gate 22 goes ON andprovides the second enable signal ENZ2 as the control signal CON to thegate of the NMOS transistor Q3. When the main power-down signal CKEMZ ishigh, the transfer gate 22 goes OFF.

[0053] The source of the PMOS transistor Q6 is connected to a highpotential power supply and the drain of the PMOS transistor Q6 isconnected to the gate of the NMOS transistor Q3. The gate of the PMOStransistor Q6 is provided with the main power-down signal CKEMZ by wayof the inverter circuit 23. Thus, if the main power-down signal CKEMZ ishigh, the PMOS transistor Q6 goes ON and sends a high control signal CONto the gate of the NMOS transistor Q3. That is, if either the mainpower-down signal CKEMZ or the second enable signal ENZ2 is high, thecontrol circuit 11 b sends a high control signal CON to the gate of theNMOS transistor Q3. This causes the NMOS transistor Q3 to go ON andactivates the differential amplifying circuit 11 a.

[0054] If the main power-down signal CKEMZ and the second enable signalENZ2 are both low, the control circuit 11 b provides a low controlsignal CON to the gate of the NMOS transistor Q3. This causes the NMOStransistor Q3 to go OFF and deactivates the differential amplifyingcircuit 11 a.

[0055] Accordingly, when the differential amplifying circuit 11 a isactivated, the differential amplifying circuit 11 a outputs the internalclock signal CLKSZ (first internal clock signal CLKM1) in accordancewith the first external clock signal CLK1. On the other hand, when thedifferential amplifying circuit 11 a is deactivated, the differentialamplifying circuit 11 a stops, or inhibits, the output of the internalclock signal CLKSZ (the first internal clock signal CLKM1) even if thefirst external clock signal CLK1 is being input.

[0056] As shown in FIG. 4, the second clock signal input buffer 12receives the second external clock signal CLK2 from the external deviceand outputs the second internal clock signal CLKM2, which phase issubstantially the same as the second external clock signal CLK2.Furthermore, the second clock signal input buffer 12 receives the secondenable signal ENZ2. The input buffer 12 is activated when the secondenable signal ENZ2 is high and deactivated when the second enable signalENZ2 is low.

[0057]FIG. 6 is a circuit diagram showing the second clock signal inputbuffer 12. The second clock signal input buffer 12, which is a currentmirror type differential amplifying circuit, includes a differentialamplifying portion having NMOS transistors Q7, Q8, a constant currentportion having an NMOS transistor Q9, and a current mirror portionhaving PMOS transistors Q10, Q11.

[0058] The sources of the NMOS transistors Q7, Q8 are grounded by way ofthe NMOS transistor Q9. The drain of the NMOS transistor Q7 is connectedto a high potential power supply by way of the PMOS transistor Q10. Thedrain of the NMOS transistor Q8 is connected to a high potential powersupply by way of the PMOS transistor Q11. The gates of the PMOStransistors Q10, Q11 are connected together and to the drain of the NMOStransistor Q8. The drain of the NMOS transistor Q7 is connected to theinput of the inverter circuit 24. The gate of the NMOS transistor Q7 isprovided with the second external clock signal CLK2. The gate of theNMOS transistor Q8 is provided with a reference voltage Vref. The gateof the NMOS transistor Q9 is provided with the second enable signalENZ2.

[0059] If the second enable signal ENZ2 is high, the NMOS transistor Q9goes ON and activates the second clock signal input buffer 12. If thesecond enable signal ENZ2 is low, the NMOS transistor Q9 goes OFF anddeactivates the second clock signal input buffer 12. When the secondclock signal input buffer 12 is activated, it outputs the secondinternal clock signal CLKM2 in accordance with the second external clocksignal CLK2. On the other hand, when the second clock signal inputbuffer 12 is deactivated, it stops, or inhibits, the output of thesecond internal clock signal CLKM2 even if the second external clocksignal CLK2 is being input.

[0060] As shown in FIG. 4, the power-down signal input buffer 13, whichfunctions as an external control signal input circuit, receives theexternal power-down signal CKE and outputs a main power-down signalCKEMZ, which phase is substantially the same as the external power-downsignal CKE. The buffer 13 outputs a high main power-down signal CKEMZ ifthe external power-down signal CKE is high and outputs a low main powerdown signal CKEMZ if the external power-down signal CKE is low.

[0061] The first clock signal input buffer 11 is activated by a highmain power-down signal CKEMZ and deactivated when the main power-downsignal CKEMZ and the second enable signal ENZ2 are both low.

[0062] The latch circuit 14, which functions as an internal clock signaloutput circuit, receives the main power-down signal CKEMZ and theinternal clock signal CLKSZ, which is sent from the first clock signalinput buffer 11. When the internal clock signal CLKSZ goes high, thelatch circuit 14 latches the main power-down signal CKEMZ (in a highlevel or a low level). The latched main power-down signal CKEMZ isoutput from the latch circuit 14 as the internal power-down signalCKECZ.

[0063]FIG. 7 is a circuit diagram showing the latch circuit 14, whichincludes a judgement circuit 14 a and a latch circuit 14 b. The latchcircuit 14 outputs a high internal power-down signal CKECZ if theinternal clock signal CLKSZ goes high when the main power-down signalCKEMZ is high. Further, the latch circuit 14 outputs a low internalpower-down signal CKECZ if the internal clock signal CLKSZ goes highwhen the main power-down signal CKEMZ is low.

[0064] The judgement circuit 14 a includes an amplifying portion havingNMOS transistors Q12, Q13, a constant current portion having an NMOStransistor Q14, a first output circuit 26 having a PMOS transistor Q21and an NMOS transistor Q22, and a second output circuit 27 having a PMOStransistor Q23 and an NMOS transistor Q24.

[0065] The sources of the NMOS transistors Q12, Q13 are grounded by wayof the NMOS transistor Q14. The drain of the NMOS transistor Q12 isconnected to a high potential power supply by way of an NMOS transistorQ15 and a PMOS transistor Q16. The gates of the transistors Q15, Q16 areconnected to each other. The drain of the NMOS transistor Q13 isconnected to a high potential power supply by way of an NMOS transistorQ17 and a PMOS transistor Q18. The gates of the transistors Q17, Q18 areconnected to each other. The PMOS transistors Q16, Q18 are eachconnected in parallel to PMOS transistors Q19, Q20, respectively.

[0066] The gates of the NMOS transistor Q14 and the PMOS transistorsQ19, Q20 are provided with the internal clock signal CLKSZ. The gate ofthe NMOS transistor Q12 is provided with the main power-down signalCKEMZ. The gate of the NMOS transistor Q13 is also provided with themain power-down signal CKEMZ by way of an inverter circuit 25.

[0067] The drain of the NMOS transistor Q15 is connected to the gate ofthe PMOS transistor Q21 in the first output circuit 26 and to the gateof the NMOS transistor Q24 in the second output circuit 27 by way of aninverter circuit 28. The drain of the NMOS transistor Q15 is alsoconnected to the gates of the NMOS transistor Q17 and the PMOStransistor Q18.

[0068] The drain of the NMOS transistor Q17 is connected to the gate ofthe PMOS transistor Q23 in the second output circuit 27 and to the gateof the NMOS transistor Q22 in the first output circuit 26 by way of aninverter circuit 29. The drain of the NMOS transistor Q17 is alsoconnected to the gates of the NMOS transistor Q15 and the PMOStransistor Q16.

[0069] The NMOS transistors Q12, Q13 are connected in series to the NMOStransistors Q25, Q26, respectively. The gate of the NMOS transistor Q25is provided with the output signal of the inverter circuit 28, and thegate of the NMOS transistor Q26 is provided with the output signal of aninverter circuit 29.

[0070] In the judgement circuit 14 a, the NMOS transistor Q14 goes ONwhen the internal clock signal CLKSZ is high. The NMOS transistor Q12goes ON and the NMOS transistor Q13 goes OFF when the main power-downsignal CKEMZ (the external power-down signal CKE) is high. In thisstate, the potential at the drain of the NMOS transistor Q15 goes lowand the potential at the drain of the NMOS transistor Q17 goes high.Thus, the PMOS transistor Q21 goes ON, the NMOS transistor Q22 goes OFF,and the first output circuit 26 outputs a high signal. Furthermore, thePMOS transistor Q23 goes OFF, the NMOS transistor Q24 goes ON, and thesecond output circuit 27 outputs a low signal. In this state, a highoutput signal from the inverter circuit 28 causes the NMOS transistorQ25 to go ON, and a low output signal from the inverter circuit 29causes the NMOS transistor Q26 to go OFF. In addition, the PMOStransistor Q16 goes OFF, the NMOS transistor Q15 goes ON, the PMOStransistor Q18 goes ON, and the NMOS transistor Q17 goes OFF.

[0071] If the internal clock signal CLKSZ goes low in this state, theNMOS transistor Q14 goes OFF, the PMOS transistors Q19, Q20 go ON, andthe drains of the NMOS transistors Q15, Q17 are both set at a highlevel. As a result, the transistors Q21-Q24 go OFF and the first andsecond output circuits 26, 27 are set to a high impedance state.

[0072] Afterward, if the internal clock signal CLKSZ goes high, thedrain of the NMOS transistor Q15 goes low and the drain of the NMOStransistor Q17 remains high. Thus, the first output circuit 26 outputs ahigh signal and the second output circuit 27 outputs a low signal. Inother words, if the main power-down signal CKEMZ (external power-downsignal CKE) is high, the first output circuit 26 outputs a high signaland the second output circuit 27 outputs a low signal each time theinternal clock signal CLKSZ goes high. Furthermore, the first and secondoutput circuits 26, 27 are set at high impedance states each time theinternal clock signal CLKSZ goes low.

[0073] When the main power-down signal CKEMZ (external power-down signalCKE) is low, the drain of the NMOS transistor Q17 goes low and the drainof the NMOS transistor Q15 remains high each time the internal clocksignal CLKSZ goes high. Thus, the first output circuit 26 outputs a lowsignal and the second output circuit 27 outputs a high signal.

[0074] In this state, if the internal clock signal CLKSZ goes low, thedrains of the NMOS transistor Q15 and the NMOS transistor Q17 are bothset to a high level, the transistors Q21-Q24 go OFF, and the first andsecond output circuits 26, 27 are set to a high impedance state.

[0075] The latch circuit 14 b includes a latch circuit 33, which isformed by inverter circuits 31, 32, and two inverter circuits 34, 35.The output terminal of the latch circuit 33 is connected to the outputterminal of the first output circuit 26. The input terminal of the latchcircuit 33 is connected to the output terminal of the second outputcircuit 27. Accordingly, the latch circuit 33 latches the signals outputfrom the first and second output circuits 26, 27 each time the internalclock signal CLKSZ goes high. In other words, if the main power-downsignal CKEMZ (the external power-down signal CKE) is high, the latchcircuit 33 latches the high signal. If the main power-down signal CKEMZ(the external power-down signal CKE) is low, the latch circuit 33latches the low signal. The latch signal of the latch circuit 33, or themain power-down signal CKEMZ (external power-down signal CKE), is outputthrough the inverter circuits 34, 35, which are connected in series, asthe internal power-down signal CKECZ.

[0076] As shown in FIG. 4, the first enable signal generating circuit 15receives the internal power-down signal CKECZ from the latch circuit 14and the internal clock signal CLKSZ from the first clock signal inputbuffer 11, holds the (high or low) internal power-down signal CKECZ inresponse to the rising of the internal clock signal CLKSZ, and providesthe held internal power-down signal CKECZ to the second enable signalgenerating circuit 16 as the first enable signal ENZ1.

[0077]FIG. 8 is a circuit diagram showing the first enable signalgenerating circuit 15, which includes a control circuit 15 a and a latchcircuit 15 b. The control circuit 15 a is provided with a transfer gate36 having a PMOS transistor and an NMOS transistor and two invertercircuits 37, 38.

[0078] The PMOS transistor gate of the transfer gate 36 receives theinternal clock signal CLKSZ. The NMOS transistor gate of the transfergate 36 receives the internal clock signal CLKSZ by way of the invertercircuit 37. When the internal clock signal CLKSZ is low, the transfergate 36 goes ON and the internal power-down signal CKECZ is sent to thelatch circuit 15 b through the inverter circuit 38 and the transfer gate36. When the internal clock signal CLKSZ is high, the transfer gate 36goes OFF and the internal power-down signal CKECZ is not provided to thelatch circuit 15 b.

[0079] The latch circuit 15 b includes inverter circuits 39, 40. Theinput terminal of the latch circuit 15 b is connected to the outputterminal of the transfer gate 36. The latch circuit 15 b latches theinternal power-down signal CKECZ each time the internal clock signalCLKSZ goes high and outputs the latched internal power-down signal CKECZas the first enable signal ENZ1. In other words, when the internalpower-down signal CKECZ (the external power-down signal CKE) is high,the latch circuit 15 b outputs a high first enable signal ENZ1. If theinternal power-down signal CKECZ (the external power-down signal CKE) islow, the latch circuit 15 b outputs a low first enable signal ENZ1.

[0080] As shown in FIG. 4, the second enable signal generating circuit16 receives the first enable signal ENZ1 from the first enable signalgenerating circuit 15 and the internal clock signal CLKSZ from the firstclock signal input buffer 11, holds the first enable signal ENZ1 inresponse to the rising of the internal clock signal CLKSZ, and outputsthe held first enable signal ENZ1 as the second enable signal ENZ2.

[0081]FIG. 9 is a circuit diagram showing the second enable signalgenerating circuit 16, which includes a control circuit 16 a and a latchcircuit 16 b. The control circuit 16 a is provided with a transfer gate42 having a PMOS transistor and an NMOS transistor and two invertercircuits 43, 44.

[0082] The NMOS transistor gate of the transfer gate 42 receives theinternal clock signal CLKSZ. The PMOS transistor gate of the transfergate 42 receives the internal clock signal CLKSZ by way of the invertercircuit 43. When the internal clock signal CLKSZ is high, the transfergate 42 goes ON and the first enable signal ENZ1 is sent to the latchcircuit 16 b through the inverter circuit 44 and the transfer gate 42.When the internal clock signal CLKSZ is low, the transfer gate 42 goesOFF and the first enable signal ENZ1 is not provided to the latchcircuit 16 b.

[0083] The latch circuit 16 b includes inverter circuits 45, 46. Theinput terminal of the latch circuit 16 b is connected to the outputterminal of the transfer gate 42. The latch circuit 16 b latches thefirst enable signal ENZ1 each time the internal clock signal CLKSZ goeslow and outputs the latched first enable signal ENZ1 as the secondenable signal ENZ2. In other words, when the first enable signal ENZ1(the internal power-down signal CKECZ) is high, the latch circuit 16 boutputs a high second enable signal ENZ2. If the first enable signalENZ1 (the internal power-down signal CKECZ) is low, the latch circuit 16b outputs a low second enable signal ENZ2.

[0084] As shown in FIG. 4, the first gate circuit 17, which ispreferably a two input AND circuit, receives the internal clock signalCLKSZ from the first clock signal input buffer 11 and the first enablesignal ENZ1 from the first enable signal generating circuit 15, andoutputs the internal clock signal CLKSZ as the first internal clocksignal CLKM1 when the first enable signal ENZ1 is high. Furthermore, thefirst gate circuit 17 does not output the internal clock signal CLKSZwhen the first enable signal ENZ1 is low.

[0085] The operation of the internal clock signal generating circuit 10a will now be described.

[0086] The power-down signal input buffer 13 receives a high externalpower-down signal CKE and outputs a high main power-down signal CKEMZ.The first clock signal input buffer 11 is activated by the high mainpower-down signal CKEMZ and provides the first external clock signalCLK1 as the internal clock signal CLKSZ to the latch circuit 14, thefirst enable signal generating circuit 15, the second enable signalgenerating circuit 16, and the first gate circuit 17.

[0087] The latch circuit 14 outputs a high internal power-down signalCKECZ. The first enable signal generating circuit 15 outputs a highfirst enable signal ENZ1. The second enable signal generating circuit 16outputs a high second enable signal ENZ2. Thus, the first gate circuit17 outputs the internal clock signal CLKSZ as the first internal clocksignal CLKM1. The second clock signal input buffer 12 is activated whenthe second enable signal ENZ2 goes high and outputs the second externalclock signal CLK2 as the second internal clock signal CLKM2.

[0088] When the external power-down signal CKE goes low, the power-downsignal input buffer 13 outputs a low main power-down signal CKEMZ.Despite the falling of the main power-down signal CKEMZ, the high secondenable signal ENZ2 keeps the first clock signal input buffer 11 in anactivated state. Thus, the first clock signal CLK1 is continuouslyoutput as the internal clock signal CLKSZ by the first clock signalinput buffer 11.

[0089] After the main power-down signal CKEMZ goes low, the latchcircuit 14 latches the low main power-down signal CKEMZ in response tothe rising of the internal clock signal CLKSZ and provides the firstenable signal generating circuit 15 with a low internal power-downsignal CKECZ.

[0090] When the internal clock signal CLKSZ falls after the latchcircuit 14 latches the low main power-down signal CKEMZ, the firstenable signal generating circuit 15 latches the low internal power-downsignal CKECZ and provides the second enable signal generating circuit 16and the first gate circuit 17 with a low first enable signal ENZ1.

[0091] The first gate circuit 17 invalidates the first internal clocksignal CLKM1 in response to the low first enable signal ENZ1. That is,as shown in FIG. 10, the falling of the internal clock signal CLKSZafter the latching of the low main power-down signal CKEMZ invalidatesthe first internal clock signal CLKM1.

[0092] When the internal clock signal CLKSZ rises after the first enablesignal generating circuit 15 latches the low internal power-down signalCKECZ, the second enable signal generating circuit 16 latches the lowfirst enable signal ENZ1 and provides the first and second clock signalinput buffers 11, 12 with a low second enable signal ENZ2.

[0093] The low second enable signal ENZ2 deactivates the first clocksignal input buffer 11 and invalidates the internal clock signal CLKSZ.Furthermore, the low second enable signal ENZ2 deactivates the secondclock signal input buffer 12 and invalidates the second internal clocksignal CLKM2. That is, as shown in FIG. 10, the rising of the internalclock signal CLKSZ subsequent to its falling after latching of the lowmain power-down signal CKEMZ invalidates the second internal clocksignal CLKM2. In other words, the second internal clock signal CLKM2 isinvalidated when half a cycle of the internal clock signal CLKSZ (thefirst internal clock signal CLKM1) elapses subsequent to theinvalidation of the first internal clock signal CLKM1.

[0094] When the external power-down signal CKE rises again subsequent tothe invalidation of the first and second internal clock signals CLKM1,CLKM2, the power-down signal input buffer 13 outputs a high mainpower-down signal CKEMZ. The high main power-down signal CKEMZ activatesthe first clock signal input buffer 11 and provides the latch circuit14, the first enable signal generating circuit 15, the second enablesignal generating circuit 16, and the first gate circuit 17 with theinternal clock signal CLKSZ.

[0095] The latch circuit 14 outputs a high power-down signal CKECZ. Thefirst enable signal generating circuit 15 outputs a high first enablesignal ENZ1 and the second enable signal generating circuit 16 outputs ahigh second enable signal ENZ2.

[0096] After the main power-down signal CKEMZ goes high, the latchcircuit 14 latches the high main power-down signal CKEMZ in response tothe first rising of the internal clock signal CLKSZ and provides thefirst enable signal generating circuit 15 with a high internalpower-down signal CKECZ.

[0097] When the internal clock signal CLKSZ falls after the latchcircuit 14 latches the high main power-down signal CKEMZ, the firstenable signal generating circuit 15 latches the high internal power-downsignal CKECZ and provides the second enable signal generating circuit 16and the first gate circuit 17 with a high first enable signal ENZ1.

[0098] The first gate circuit 17 outputs the first internal clock signalCLKM1 in response to the high first enable signal ENZ1. That is, thefalling of the internal clock signal CLKSZ after the latching of the lowmain power-down signal CKEMZ validates the first internal clock signalCLKM1.

[0099] When the internal clock signal CLKSZ rises after the first enablesignal generating circuit 15 latches the high internal power-down signalCKECZ, the second enable signal generating circuit 16 latches the highfirst enable signal ENZ1 and provides the first and second clock signalinput buffers 11, 12 with a high second enable signal ENZ2.

[0100] The high second enable signal ENZ2 activates the second clocksignal input buffer 12 and causes the second internal clock signal CLKM2to be output. That is, the rising of the internal clock signal CLKSZsubsequent to its falling after latching of the high main power-downsignal CKEMZ validates the second internal clock signal CLKM2. In otherwords, the second internal clock signal CLKM2 is validated when half acycle of the internal clock signal CLKSZ (the first internal clocksignal CLKM1) elapses subsequent to the validation of the first internalclock signal CLKM1.

[0101] The characteristics of the internal clock signal generatingcircuit 10 a will now be described.

[0102] (1) When the external power-down signal CKE (main power-downsignal CKEMZ) falls, the first internal clock signal CLKM1 isinvalidated half a cycle earlier than the second internal clock signalCLKM2. Furthermore, when the external power-down signal CKE (the mainpower-down signal CKEMZ) rises, the first internal clock signal CLKM1 isvalidated half a cycle earlier than the second internal clock signalCLKM2. Accordingly, the internal clock signal generating circuit 10 aalways validates and invalidates the first and second clock signalsCLKM1, CLKM2 with a constant relationship regardless of the timing inwhich the external power-down signal CKE shifts between a high level anda low level.

[0103] (2) The first clock signal input buffer 11 remains activatedduring the period immediately after the external power-down signal CKE(the main power-down signal CKEMZ) falls. The internal clock signalCLKSZ provided by the first clock signal input buffer 11 then causes thelatch circuit 14 to output a low internal power-down signal CKECZ.Furthermore, the first enable signal generating circuit 15 outputs a lowfirst enable signal ENZ1 in response to the falling of the internalclock signal CLKSZ. After half a cycle elapses from the falling of theinternal clock signal CLKSZ, the second enable signal generating circuit16 latches the first enable signal ENZ1 in response to the rising of theinternal clock signal CLKSZ and outputs a low second enable signal ENZ2.

[0104] Accordingly, the first internal clock signal CLKM1 is alwaysinvalidated earlier by half a cycle than the second internal clocksignal CLKM2 when the external power-down signal CKE (the mainpower-down signal CKEMZ) falls.

[0105] (3) The first clock signal input buffer 11 is activatedimmediately after the external power-down signal CKE (main power-downsignal CKEMZ) rises. When the internal clock signal CLKSZ provided bythe first clock signal input buffer 11 rises, the latch circuit 14outputs a high internal power-down signal CKECZ. Furthermore, the firstenable signal generating circuit 15 outputs a high first enable signalENZ1 in response to the falling of the internal clock signal CLKSZ.After half a cycle elapses from the falling of the internal clock signalCLKSZ, the second enable signal generating circuit 16 latches the firstenable signal ENZ1 in response to the rising of the internal clocksignal CLKSZ and outputs a high second enable signal ENZ2.

[0106] Accordingly, the first internal clock signal CLKM1 is alwaysvalidated earlier by half a cycle than the second internal clock signalCLKM2 when the external power-down signal CKE (main power-down signalCKEMZ) rises.

[0107]FIG. 11 is a circuit diagram showing another second enable signalgenerating circuit 160, which includes a control circuit 160 a and alatch circuit 160 b. The latch circuit 160 b is provided with a NORcircuit 51 in lieu of the inverter circuit 46 shown in FIG. 9. The NORcircuit 51, which is preferably a two input NOR circuit, has a firstinput terminal connected to the output terminal of the transfer gate 42and a second input terminal connected to the output terminal of aninverter circuit 44 of the control circuit 160 a. Thus, the signal fromthe inverter circuit 44 (an inverted first enable signal ENZ1) is sentdirectly to the second input terminal of the NOR circuit 51 withoutpassing through the transfer gate 42.

[0108] The second enable signal generating circuit 160 immediatelylatches the first enable signal ENZ1, which is sent from the firstenable signal generating circuit 15, in response to the falling of theinternal clock signal CLKSZ and outputs the second enable signal ENZ2.Thus, as shown in FIG. 10, the shifting of the second enable signalENZ2, which is output by the second enable signal generating circuit160, occurs as shown by the dashed lines. This results in the secondclock signal CLKM2, which is output by the second clock signal inputbuffer 12, having a waveform shown by the dashed lines. In other words,the first internal clock signal CLKM1 always rises earlier by half acycle than the second internal clock signal CLKM2. In this case, thefirst internal clock signal CLKM1 is invalidated when low, and thesecond internal clock signal CLKM2 is invalidated when high.

[0109] [Second Embodiment]

[0110]FIG. 12 is a schematic block diagram showing an internal clocksignal generating circuit 10 b according to a second embodiment of thepresent invention. In the internal clock signal generating circuit 10 b,the second enable signal generating circuit 16 latches the first enablesignal ENZ1 when a second clock signal CLKSZ2, which phase issubstantially the same as the second external clock signal CLK2 is high,and the first enable signal generating circuit 15 latches the internalpower-down signal CKECZ when the first internal clock signal CLKM1 ishigh. In this case, when the external power-down signal CKE (the mainpower-down signal CKEMZ) falls, the first internal clock signal CLKM1 isalways invalidated earlier by half a cycle than the second internalclock signal CLKM2. Furthermore, when the external power-down signal CKE(the main power-down signal CKEMZ) rises, the first internal clocksignal CLKM1 is always validated earlier by half a cycle than the secondinternal clock signal CLKM2.

[0111] In the second embodiment, the second clock signal input buffer 12is activated when either a main-power down signal CKEMZ, which is sentfrom the power-down signal input buffer 13, or a second enable signalENZ2, which is sent from the second enable signal generating circuit 16,is high. The second clock signal input buffer 12 is deactivated when themain power-down signal CKEMZ and the second enable signal ENZ2 are bothlow.

[0112] The internal clock signal generating circuit 10 b includes asecond gate circuit 18 for receiving the second clock signal CLKSZ2 andthe second enable signal ENZ2 and generating the second internal clocksignal CLKM2.

[0113] [Third Embodiment]

[0114]FIG. 13 is a schematic block diagram showing an internal clocksignal generating circuit 10 c according to a third embodiment of thepresent invention. In the internal clock signal generating circuit 10 c,the second enable signal generating circuit 16 is eliminated and asecond gate circuit 52 is provided. The second gate circuit 52 controlsthe output of the second internal clock signal CLKM2, which is providedby the second clock signal input buffer 12, in accordance with the firstenable signal ENZ1 output, which is provided by the first enable signalgenerating circuit 15. The second gate circuit 52 is preferably a twoinput NAND circuit. That is, the second gate circuit 52 has a firstinput terminal, which receives the second internal clock signal CLKM2sent from the second clock signal input buffer 12 by way of an inverter60, and a second input terminal, which receives the first enable signalENZ1 sent from the first enable signal generating circuit 15.

[0115] The first enable signal ENZ1 sent from the first enable signalgenerating circuit 15 is used to activate or deactivate the first andsecond clock signal input buffers 11, 12.

[0116]FIG. 14 is a timing chart showing the operation of the internalclock signal generating circuit 10 c. In the third embodiment, the firstinternal clock signal CLKM1 is always validated and invalidated a halfcycle earlier than the second internal clock signal CLKM2. In this case,the first internal clock signal CLKM1 is invalidated when low, and thesecond internal clock signal CLKM2 is invalidated when high. Since thesecond enable signal generating circuit 16 is eliminated, the clocksignal generating circuit 10 c occupies less space than that of FIG. 4.

[0117] [Fourth Embodiment]

[0118]FIG. 15 is a schematic block diagram showing an internal clocksignal generating circuit 10 d according to a fourth embodiment of thepresent invention. In the internal clock signal generating circuit 10 d,the second enable signal generating circuit 16 receives the internalpower-down signal CKECZ from the latch circuit 14 and the secondinternal clock signal CLKM2 from the second clock signal input buffer12. Furthermore, a second gate circuit 53 is provided to control theoutput of the second clock signal CLKSZ2 as the second internal clocksignal CLKM2 sent from the second clock signal input buffer 12 via aninverter 55, in accordance with the second enable signal ENZ2. A thirdgate circuit 54 receives the internal power-down signal CKECZ from thelatch circuit 14, and the second enable signal ENZ2, which is sent fromthe second enable signal generating circuit 16, to generate a thirdenable signal ENZ3. The second gate circuit 53 is preferably a two inputAND circuit. The third gate circuit 54 is preferable a two input ORcircuit. The first and second clock signal input buffers 11, 12 receivethe third enable signal ENZ3 from the third gate (OR) circuit 54.

[0119]FIG. 16 is a timing chart showing the operation of the internalclock signal generating circuit 10 d. The second enable signalgenerating circuit 16 latches the internal power-down signal CKECZ sentfrom the latch circuit 14 in response to the rising of the internalclock signal sent from the second clock signal input buffer 12. That is,the second enable signal generating circuit 16 latches the internalpower-down signal CKECZ from the latch circuit 14 at substantially thesame timing as the first enable signal generating circuit 15. Thus, thethird enable signal ENZ3 is sent to the first and second clock signalinput buffers 11, 12 at substantially the same timing as the first orsecond enable signals ENZ1 or ENZ2. Accordingly, the first internalclock signal CLKM1 is always validated or invalidated a half cycleearlier than the second internal clock signal CLKM2.

[0120] It should be apparent to those skilled in the art that thepresent invention may be embodied in many other specific forms withoutdeparting from the spirit or scope of the invention. Particularly, itshould be understood that the present invention may be embodied in thefollowing forms.

[0121] The present invention may be embodied in a semiconductorintegrated circuit, such as a semiconductor memory device or a signalprocessing device, which includes an SDRAM for providing clock signalsof different phases to a plurality of internal circuit sections.

[0122] The present invention may be embodied in a generating circuitthat generates three or more internal clock signals, each having a phasewhich differs from the others.

[0123] The phase difference between the first and second internal clocksignals CLKM1, CLKM2 is not limited to 180°.

[0124] The present examples and embodiments are to be considered asillustrative and not restrictive, and the invention is not to be limitedto the details given herein, but may be modified within the scope andequivalence of the appended claims.

What is claimed is:
 1. A semiconductor integrated circuit comprising: aplurality of clock signal input circuits, each receiving a respectiveone of plurality of external clock signals and generating a respectiveone of plurality of internal clock signals; an external control signalinput circuit for receiving an external control signal and generating aninternal control signal; and an output control circuit for receiving theinternal control signal from the external control signal input circuitand controlling the output of the internal clock signals in accordancewith changes in the internal control signal.
 2. The integrated circuitaccording to claim 1 , wherein the internal control signal shiftsbetween an active state and an inactive state, and wherein the outputcontrol circuit controls the output of the internal clock signals suchthat the internal clock signals always have a substantially constantrelationship when the internal control signal shifts from an inactivestate to an active state.
 3. The integrated circuit according to claim 1, wherein the internal control signal shifts between an active state andan inactive state, and wherein the output control circuit controls theoutput of the internal clock signals such that the internal clocksignals always have a substantially constant relationship when theinternal control signal shifts from an active state to an inactivestate.
 4. The integrated circuit according to claim 1 , wherein theinternal control signal shifts between an active state and an inactivestate, and wherein the output control circuit controls the output of theinternal clock signals such that the internal clock signals always havea substantially constant relationship when the internal control signalshifts from an inactive state to an active state and from an activestate to an inactive state.
 5. The integrated circuit according to claim1 , wherein the plurality of clock signal input circuits includes afirst clock signal input circuit and a second clock signal inputcircuit, and wherein the output control circuit includes: a latchcircuit connected to the external control signal input circuit and thefirst clock signal input circuit, wherein the latch circuit latches theinternal control signal in response to a first internal clock signalgenerated by the first clock signal input circuit; a first enable signalgenerating circuit connected to the latch circuit and the first clocksignal input circuit, wherein the first enable signal generating circuitholds the latched internal control signal in response to the firstinternal clock signal and generates a first enable signal; a gatecircuit connected to the first enable signal generating circuit and thefirst clock signal input circuit, wherein the gate circuit controls theoutput of the first internal clock signal in accordance with the firstenable signal; and a second enable signal generating circuit connectedto the first enable signal generating circuit and the second clocksignal input circuit, wherein the second enable signal generatingcircuit holds the first enable signal in response to the first internalclock signal and generates a second enable signal for selectivelyactivating and deactivating the second clock signal input circuit. 6.The integrated circuit according to claim 1 , wherein the plurality ofclock signal input circuits includes a first clock signal input circuitand a second clock signal input circuit, and wherein the output controlcircuit includes: a latch circuit connected to the external controlsignal input circuit and the first clock signal input circuit, whereinthe latch circuit latches the internal control signal in response to afirst internal clock signal generated by the first clock signal inputcircuit; a gate circuit connected to the first clock signal inputcircuit and the first enable signal generating circuit, wherein the gatecircuit controls the output of the first internal clock signal inaccordance with the first enable signal; a first enable signalgenerating circuit connected to the latch circuit and the gate circuit,wherein the first enable signal generating circuit holds the latchedinternal control signal in response to the output controlled firstinternal clock signal and generates a first enable signal; and a secondenable signal generating circuit connected to the first enable signalgenerating circuit and the second clock signal input circuit, whereinthe second enable signal generating circuit holds the first enablesignal in response to the second internal clock signal and generates asecond enable signal for selectively activating and deactivating thesecond clock signal input circuit.
 7. The integrated circuit accordingto claim 1 , wherein the plurality of clock signal input circuitsincludes a first clock signal input circuit and a second clock signalinput circuit, and wherein the output control circuit includes: a latchcircuit connected to the external control signal input circuit and thefirst clock signal input circuit, wherein the latch circuit latches theinternal control signal in response to a first internal clock signal; anenable signal generating circuit connected to the latch circuit, thefirst clock signal input circuit, and the second clock signal inputcircuit, wherein the enable signal generating circuit holds the latchedinternal control signal in response to the first internal clock signaland generates an enable signal for selectively activating anddeactivating the first and second clock signal input circuits; a firstgate circuit connected to the enable signal generating circuit and thefirst clock signal input circuit, wherein the first gate circuitcontrols the output of the first internal clock signal in accordancewith the enable signal; and a second gate circuit connected to theenable signal generating circuit and the second clock signal inputcircuit, wherein the second gate circuit controls the output of thesecond internal clock signal in accordance with the enable signal. 8.The integrated circuit according to claim 1 , wherein the plurality ofclock signal input circuits includes a first clock signal input circuitand a second clock signal input circuit, and wherein the output controlcircuit includes: a latch circuit connected to the external controlsignal input circuit and the first clock signal input circuit, whereinthe latch circuit latches the internal control signal in response to afirst internal clock signal generated by the first clock signal inputcircuit; a first enable signal generating circuit connected to the latchcircuit and the first clock signal input circuit, wherein the firstenable signal generating circuit holds the latched internal controlsignal in response to the first internal clock signal and generates afirst enable signal, the first clock signal input circuit beingselectively activated and deactivated by the first enable signal; asecond enable signal generating circuit connected to the latch circuitand the second clock signal input circuit, wherein the second enablesignal generating circuit holds the latched internal control signal inresponse to the second internal clock signal and generates a secondenable signal for selectively activating and deactivating the secondclock signal input circuit; a first gate circuit connected to the firstenable signal generating circuit and the first clock signal inputcircuit, wherein the first gate circuit controls the output of the firstinternal clock signal in accordance with the first enable signal; and asecond gate circuit connected to the second enable signal generatingcircuit and the second clock signal input circuit, wherein the secondgate circuit controls the output of the second internal clock signal inaccordance with the second enable signal.
 9. A semiconductor integratedcircuit comprising: a first clock signal input buffer and a second clocksignal input buffer for receiving first and second external clocksignals, each having a different phase, and generating first and secondinternal clock signals, each having a different phase, respectively; apower-down signal input buffer for receiving an external power-downsignal and generating an internal power-down signal; and an outputcontrol circuit for receiving the internal power-down signal from thepower-down signal input buffer, and controlling the output of the firstand second internal clock signals in accordance with changes in theinternal power-down signal.
 10. The integrated circuit according toclaim 9 , wherein the internal power-down signal shifts between anactive state and an inactive state, and wherein the output controlcircuit controls the output of the first and second internal clocksignals such that the first and second internal clock signals alwayshave a substantially constant relationship when the internal power-downsignal shifts from an inactive state to an active state.
 11. Theintegrated circuit according to claim 9 , wherein the internalpower-down signal shifts between an active state and an inactive state,and wherein the output control circuit controls the output of the firstand second internal clock signals such that the first and secondinternal clock signals always have a substantially constant relationshipwhen the internal power-down signal shifts from an active state to aninactive state.
 12. The integrated circuit according to claim 9 ,wherein the internal power-down signal shifts between an active stateand an inactive state, and wherein the output control circuit controlsthe output of the first and second internal clock signals such that thefirst and second internal clock signals always have a substantiallyconstant relationship when the internal power-down signal shifts from aninactive state to an active state and from an active state to aninactive state.
 13. The integrated circuit according to claim 9 ,wherein the internal power-down signal shifts between an active stateand an inactive state, and wherein the output control circuit validatesthe output of the second internal clock signal after validating theoutput of the first internal clock signal when the internal power-downsignal shifts from an inactive state to an active state.
 14. Theintegrated circuit according to claim 9 , wherein the internalpower-down signal shifts between an active state and an inactive state,and wherein the output control circuit invalidates the output of thesecond internal clock signal after invalidating the output of the firstinternal clock signal when the internal power-down signal shifts from anactive state to an inactive state.
 15. The integrated circuit accordingto claim 9 , wherein the output control circuit includes: a latchcircuit connected to the power-down signal input buffer and the firstclock signal input buffer, wherein the latch circuit latches theinternal power-down signal in response to the first internal clocksignal; and an enable signal generating circuit connected to the latchcircuit and the first clock signal input buffer, wherein the enablesignal generating circuit holds the latched internal power-down signalin response to the first internal clock signal and generates an enablesignal for selectively activating and deactivating the first and secondclock signal input buffers.
 16. The integrated circuit according toclaim 15 , wherein the output control circuit further includes: a firstgate circuit connected to the enable signal generating circuit and thefirst clock signal input buffer, wherein the first gate circuit controlsthe output of the first internal clock signal in accordance with theenable signal; and a second gate circuit connected to the enable signalgenerating circuit and the second clock signal input buffer, wherein thesecond gate circuit controls the output of the second internal clocksignal in accordance with the enable signal.
 17. The integrated circuitaccording to claim 9 , wherein the output control circuit includes: alatch circuit connected to the power-down signal input buffer and thefirst clock signal input buffer, wherein the latch circuit latches theinternal power-down signal in response to the first internal clocksignal; a first enable signal generating circuit connected to the latchcircuit and the first clock signal input buffer, wherein the firstenable signal generating circuit holds the latched internal power-downsignal in response to the first internal clock signal and generates afirst enable signal; a gate circuit connected to the first enable signalgenerating circuit and the first clock signal input buffer, wherein thegate circuit controls the output of the first internal clock signal inaccordance with the first enable signal; and a second enable signalgenerating circuit connected to the first enable signal generatingcircuit and the second clock signal input buffer, wherein the secondenable signal generating circuit holds the first enable signal inresponse to the first internal clock signal and generates a secondenable signal for selectively activating and deactivating the secondclock signal input buffer.
 18. The integrated circuit according to claim17 , wherein, after the first enable signal generating circuit generatesthe first enable signal in response to an initial first internal clocksignal, the second enable signal generating circuit generates the secondenable signal in response to a subsequent first internal clock signal.19. The integrated circuit according to claim 17 , wherein the secondenable signal generating circuit generates the second enable signalafter half a cycle of a clock elapses from when the first enable signalis generated.
 20. The integrated circuit according to claim 17 , whereinthe second enable signal generating circuit generates the second enablesignal such that it is substantially synchronized with the first enablesignal.
 21. The integrated circuit according to claim 17 , wherein thefirst and second enable signal generating circuits each holds theinternal power-down signal and the first enable signal in response tothe same first internal clock signal.
 22. The integrated circuitaccording to claim 9 , wherein the output control circuit includes: alatch circuit connected to the power-down signal input buffer and thefirst clock signal input buffer, wherein the latch circuit latches theinternal power-down signal in response to the first internal clocksignal; a gate circuit connected to the first clock signal input buffer,wherein the gate circuit controls the output of the first internal clocksignal in accordance with the first enable signal; a first enable signalgenerating circuit connected to the gate circuit and the latch circuit,wherein the first enable signal generating circuit holds the latchedinternal power-down signal in response to the output controlled firstinternal clock signal and generates the first enable signal; and asecond enable signal generating circuit connected to the first enablesignal generating circuit and the second clock signal input buffer,wherein the second enable signal generating circuit holds the firstenable signal in response to the second internal clock signal andgenerates a second enable signal for selectively activating anddeactivating the second clock signal input buffer.
 23. The integratedcircuit according to claim 9 , wherein the output control circuitincludes: a latch circuit connected to the power-down signal inputbuffer and the first clock signal input buffer, wherein the latchcircuit latches the internal power-down signal in response to the firstinternal clock signal; a first enable signal generating circuitconnected to the first clock signal input buffer and the latch circuit,wherein the first enable signal generating circuit holds the latchedinternal power-down signal in response to the first internal clocksignal to generate a first enable signal; a second enable signalgenerating circuit connected to the latch circuit and the second clocksignal input buffer, wherein the second enable signal generating circuitholds the latched internal power-down signal in response to the secondinternal clock signal to generate a second enable signal; a first gatecircuit connected to the first enable signal generating circuit and thefirst clock signal input buffer, wherein the first gate circuit controlsthe output of the first internal clock signal in accordance with thefirst enable signal; a second gate circuit connected to the secondenable signal generating circuit and the second clock signal inputbuffer, wherein the second gate circuit controls the output of thesecond internal clock signal in accordance with the second enablesignal; and a third gate circuit connected to the latch circuit and thesecond enable signal generating circuit, wherein the third gate circuitreceives the latched internal power-down signal and the second enablesignal to provide the first and second clock signal input buffers with athird enable signal.
 24. The integrated circuit according to claim 23 ,wherein the latch circuit latches the internal power-down signal inresponse to the rising edge of the first internal clock signal, whereinthe first enable signal generating circuit holds the latched internalpower-down signal in response to the rising edge of the first internalclock signal, and the second enable signal generating circuit holds thelatched internal power-down signal in response to the rising edge of thesecond internal clock signal.
 25. A semiconductor integrated circuit,comprising: a plurality of clock signal input circuits, including atleast a first clock signal input circuit and a second clock signal inputcircuit, for receiving a respective plurality of external clock signals,and generating a respective plurality of internal clock signalstherefrom; an external control signal input circuit for receiving anexternal control signal and generating an internal control signal usedto activate the plurality of clock signal input circuits; a latchcircuit connected to the external control signal input circuit and thefirst clock signal input circuit for latching the internal controlsignal in response to a first internal clock signal generated by thefirst clock signal input circuit; a first enable signal generatingcircuit, connected to the latch circuit and the first clock signal inputcircuit, for holding the latched internal control signal in response tothe first internal clock signal and generating a first enable signal; agate circuit, connected to the first enable signal generating circuitand the first clock signal input circuit, for receiving the first enablesignal and the first clock signal and controlling the output of thefirst clock signal in accordance with the first enable signal; and asecond enable signal generating circuit, connected to the first enablesignal generating circuit and the first clock signal input circuit, forreceiving the first enable signal and the first internal clock signaland generating a second enable signal, wherein the second enable signalis provided to the first and second clock signal input circuits tocontrol the output of the first and second internal clock signals.